There is a growing overlap between PLDI and ISCA, and this workshop is convened to bring together people in that overlap. The subject coverage would be supporting ISCA-style hardware development via new programming languages, compilers, formal-verification tools, synthesis approaches, and so forth. Architecture is a relatively stodgy area, especially in industry, when it comes to adoption of new tools, and we would aim to provide a little more of a nudge to architects to try new tools, while also exposing PL experts to challenges they may not have been aware of in an adjacent community. More keywords of high interest lately to both communities include security (including side channels), weak memory models, testing, debugging, optimization, and hardware-software codesign. General approaches already being considered across this disciplinary boundary include domain-specific languages (embedded or freestanding), metaprogramming, partial evaluation, SMT solvers, proof assistants, model checking, symbolic execution, type systems, and mechanized semantics.
Sat 17 JunDisplayed time zone: Eastern Time (US & Canada) change
11:20 - 12:30
|Tags: A Framework for Distributed Event Ordering|
|Stellar: A DSL to Build and Explore Sparse Accelerators|
|PEak: A Single Source of Truth for Hardware Design and Verification|
|Challenges with Hardware-Software Co-design for Sparse Machine Learning on Streaming Dataflow|
14:00 - 15:30
|They're the same picture: a software-verification flow adapted for hardware verification|
|Design for Hardware Memory Model Verification|
Yao Hsiao Stanford University, Yasas Seneviratne University of Virginia, Tommy Tracy II University of Virginia, Kevin Skadron University of Virginia, Caroline Trippel Stanford UniversityFile Attached
|Nerv: Probabilistic Dynamic Partial Order Reduction for Hardware|
|NFC:Next-generation Formal verification for high performance Caches|
|Sandia's Formal Hardware Design and Verification, Present and Future|
Noah Evans Sandia National Laboratories
|Silver Oak: Hardware Software Co-Design and Co-Verification in Coq|
16:00 - 17:50
|Novel Numerical Hardware Design Methodology - From machine readable specification to optimized RTL|
Theo Drane Intel Corporation, USA, Bill Zorn Intel Corporation, USA, Samuel Coward Imperial College London, UK / Intel CorporationFile Attached
|Mixed-Abstraction HDLs and A Discussion on Other Aspects of HDL Design|
Vighnesh Iyer University of California, Berkeley, Borivoje Nikolic University of California, BerkeleyFile Attached
|New Embedded DSLs for Hardware Design and Verification|
Vighnesh Iyer University of California, Berkeley, Kevin Laeufer UC Berkeley, Young-Jin Park University of California, Berkeley, Rohit Agarwal University of California, Berkeley, Lixiang Yin University of California, Berkeley, Bryan Ngo University of California, Berkeley, Oliver Yu University of California, Berkeley, Koushik Sen University of California at Berkeley, Borivoje Nikolic University of California, BerkeleyFile Attached
|Fearless Hardware Design|
Rachit Nigam Cornell University
|Library-based Compartmentalisation on CHERI|
|Non-Newtonian Hardware Design for Longevity|
|On the Generality of Matrix Multiplication|
|ChatGPT, Make a Secure Malloc for me|
Call for Talks
TLDR: We are collecting position papers proposing talks about big ideas and research projects (and maybe sufficiently interesting tools that are “just engineering”) within the workshop scope. There are no associated formally published papers, and we aim to encourage discussion at and after the workshop. Contributed talk slots likely won’t be longer than 30 minutes.
PLARCH’23 is co-located with both ISCA and PLDI, within the larger FCRC experience.
Submit your 2-page position paper via HotCRP. Important dates:
- Paper submission: April 28th, 2023 (Anywhere on Earth)
- Author Notification: May 12th, 2023
- Workshop: June 17th, 2023
Scope. PLARCH is a venue for discussion, debate, and brainstorming at the intersection of ISCA and PLDI topics. We hope to interpret that scope broadly in creating the program. Perhaps a good fundamental rule of thumb is that a project being presented at PLARCH should include technical challenges recognizable to both architecture and programming-languages researchers, though the challenges could be significantly greater on one of those sides.
One mad lib-style recipe to generate an in-scope topic could be to settle on
- language design, compilers, debuggers, testing tools, profilers, formal verification, (program) synthesis, …
- development of computer processors, memory systems, accelerators, networking hardware, …
PLARCH is not a conference, and we’re excited to hear compelling talks in categories like:
- Early, in-progress research snapshots
- Experience reports
- Essays advocating for or against a general approach
- Retrospectives on past efforts
- Calls for solutions to open challenges in the area (questions without answers)
- Demonstrations of real systems (to be shown off in live demos at the workshop)
The primary goal of the workshop is to enable discussion. It will accept 2-page position papers. The workshop will allocate short time slots to the papers, each paired with a discussion following SNAPL’s discussion format: “table discussion” where small breakout groups will discuss the paper, followed by plenary Q&A.
Position paper submissions will undergo peer review by a program committee of interdisciplinary experts working on both high-level (languages, compilers, drivers) and low-level (circuit optimization, interconnect design) problems in the area.
Formatting. Papers should use the two-column the formatting guidelines for SIGPLAN conferences (the
acmart format with the
sigplan two-column option) and not exceed 2 pages, excluding references. Review is single-blind, so please include authors’ names on the submitted PDF.
Paper submission will is via HotCRP. The accepted papers will not be published in a proceedings—PDFs will instead appear on the workshop’s website.
Important guidelines. It’s standard for papers to start with a general motivation: Moore’s Law is doomed; specialized hardware is ascendant; Verilog is hard to use; etc. Please skip this part in your PLARCH position paper (and in eventual talks at the workshop). The PLARCH audience will already believe these things, so save the space & time and instead focus on your own unique ideas. As much as possible, dispose with the framing and motivation so you can focus on the technical content.
Remember that the goal at PLARCH is to stimulate discussion, not to disseminate fully polished results. So don’t be afraid to write up half-baked ideas and in-progress work: it’s OK if your submission has zero bar charts, for example.
Credit: much of this call is cribbed from a LATTE call!